Search - altera ip

[Software Engineering] altera+dpd

Description: 数字预失真在通信领域内IP核的开发文档，包括数学表达式及硬件框图-Digital Predistortion in the field of IP communications in the development of nuclear documents, including mathematical expression and hardware block diagram
Platform: | Size: 1398260 | Author: 聂华 | Hits:

[Other] leon3-altera-ep2s60-ddr

Description: The GRLIB IP Library is an integrated set of reusable IP cores, designed for system-on-chip (SOC) development. The IP cores are centered around a common on-chip bus, and use a coherent method for simulation and synthesis. The library is vendor independent, with support for different CAD tools and target technologies. A unique plug&play method is used to configure and connect the IP cores without the need to modify any global resources.-The GRLIB IP Library is an integrated set of reusable IP cores, designed for system-on-chip (SOC) developmen t. The IP cores are centered around a common on-c hip bus, and use a coherent method for simulation and syn thesis. The library is vendor independent, with support for different CAD tools and target technologies. A unique plug
Platform: | Size: 103163 | Author: 岳昆 | Hits:

[Other resource] Example-b4-2

Description: Altera IP应用设计实例  “\\Example-b4-2\\Project”目录下为设计工程  “\\Example-b4-2\\Solution”目录下为正确的解决方案，仅供读者参考
Platform: | Size: 394543 | Author: king | Hits:

[VHDL-FPGA-Verilog] pci_vhdl

Description: PCI的VHDL源码希望对大家有用！-PCI VHDL source hope useful for all!
Platform: | Size: 27648 | Author: 林建加 | Hits:

[VHDL-FPGA-Verilog] tiny16cpu_maxII

Description: 这个是专门用在ALtera第二代PLD MAXII上的16位微处理器IP核，文档齐全-this is the ALtera devoted second-generation PLD MAXII on the 16-bit microprocessor IP core, complete documentation
Platform: | Size: 240640 | Author: 李无志 | Hits:

[Embeded-SCM Develop] perl561src

Description: Altera recommends the following system configuration: * Pentium II 400 with 512-MB system memory (faster systems give better software performance) * SVGA monitor * CD-ROM drive * One or more of the following I/O ports: - USB port (if using Windows XP or Windows 2000) for USB-Blaster(TM) or MasterBlaster(TM) communications cables, or APU programming unit - Parallel port for ByteBlasterMV(TM) or ByteBlaster(TM) II download cables - Serial port for MasterBlaster communications cable * TCP/IP networking protocol installed * Windows 2000, Windows NT 4.0 with Service Pack 3 or later, or Windows XP * Internet Explorer 5.0 or later Memory & Disk Space Requirements USB开发--Altera recommends the following system configuration:* Pentium II 400 with 512-MB system memory (faster systems give better software performance)* SVGA monitor* CD-ROM drive* One or more of the following I/O ports:- USB port (if using Windows XP or Windows 2000) for USB-Blaster(TM) or MasterBlaster(TM) communications cables, or APU programming unit- Parallel port for ByteBlasterMV(TM) or ByteBlaster(TM) II download cables- Serial port for MasterBlaster communications cable* TCP/IP networking protocol installed* Windows 2000, Windows NT 4.0 with Service Pack 3 or later, or Windows XP* Internet Explorer 5.0 or later Memory & Disk Space Requirements USB development
Platform: | Size: 7300096 | Author: 周元平 | Hits:

[ARM-PowerPC-ColdFire-MIPS] Altera的IP源码8237

Description: 名鼎鼎的Synopsys公司出的8051IP Core VHDL语言编写，能被keilC51支持-renowned name of the company Synopsys 8051IP Core VHDL language, support can be keilC51
Platform: | Size: 207872 | Author: 上面的 | Hits:

[Embeded-SCM Develop] Nios_IPphone

Description: 这是基于altera的片上处理器nios 的一个IP电话终端的设计,来源altera的电子设计文章大赛.-This is based on the altera-chip processor Nios an IP telephone terminal design, the source of the electronic design altera article contest.
Platform: | Size: 190464 | Author: wokkoni | Hits:

[VHDL-FPGA-Verilog] altera_lcd_controller

Description: quartus II-sopc builder avalon总线LCD控制IPCORE-quartus II-sopc builder avalon Bus LCD controller IP CORE
Platform: | Size: 26624 | Author: 张建 | Hits:

[Other] ug_altpll

Description: altera公司的IP core，对于初学硬件描述语言，想要利用quartus软件自带的锁相环电路库函数实现自己想要的功能有些帮助-altera the IP core, for hardware description language learning, quartus want to use the software to bring their own PLL circuit to achieve the function they want to help some of the functions
Platform: | Size: 715776 | Author: 林德 | Hits:

[Other] leon3-altera-ep2s60-ddr

Description: The GRLIB IP Library is an integrated set of reusable IP cores, designed for system-on-chip (SOC) development. The IP cores are centered around a common on-chip bus, and use a coherent method for simulation and synthesis. The library is vendor independent, with support for different CAD tools and target technologies. A unique plug&play method is used to configure and connect the IP cores without the need to modify any global resources.-The GRLIB IP Library is an integrated set of reusable IP cores, designed for system-on-chip (SOC) developmen t. The IP cores are centered around a common on-c hip bus, and use a coherent method for simulation and syn thesis. The library is vendor independent, with support for different CAD tools and target technologies. A unique plug
Platform: | Size: 103424 | Author: 岳昆 | Hits:

[Software Engineering] EP2C35

Description: Altera原版PCI开发板原理图EP2C35-Altera original PCI development board schematics EP2C35
Platform: | Size: 573440 | Author: 风帆 | Hits:

[Embeded-SCM Develop] userlogicOpenI2C

Description: altera的ip核，添加后，在quartusII中可以轻松实现对i2c的控制，是fpga开发人员的必备工具之一。-altera
Platform: | Size: 12288 | Author: 朱峰 | Hits:

[VHDL-FPGA-Verilog] 2C35F672_FFT

Description: 在Altera芯片2C35F672平台上的FFT程序，采用DSPBuilder5.0，生成Verilog文件。开发环境：QuartusII5.0。-In the Altera chip 2C35F672 platform FFT procedures DSPBuilder5.0, generated Verilog file. Development Environment: QuartusII5.0.
Platform: | Size: 474112 | Author: lovenevol | Hits:

[Other] altclklock

Description: 如何给时钟倍频或者分频，以及altera提供的IP核使用方法-How to clock multiplier or divider, as well as to provide the IP of nuclear altera use
Platform: | Size: 2048 | Author: 杨华 | Hits:

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[Software Engineering] altera+dpd

[Other] leon3-altera-ep2s60-ddr

[Other resource] Example-b4-2

[VHDL-FPGA-Verilog] pci_vhdl

[VHDL-FPGA-Verilog] tiny16cpu_maxII

[Embeded-SCM Develop] perl561src

[ARM-PowerPC-ColdFire-MIPS] Altera的IP源码8237

[Embeded-SCM Develop] Nios_IPphone

[VHDL-FPGA-Verilog] altera_lcd_controller

[Other] ug_altpll

[Other] leon3-altera-ep2s60-ddr

[Software Engineering] EP2C35

[Embeded-SCM Develop] userlogicOpenI2C

[VHDL-FPGA-Verilog] 2C35F672_FFT

[Other] altclklock

[VHDL-FPGA-Verilog] altera_avalon_checksum

[Embeded-SCM Develop] altera_avalon_checksum

[VHDL-FPGA-Verilog] 15AlteraDEIP

[VHDL-FPGA-Verilog] H1wQqGvI

[Other Embeded program] altera_avalon_cy7c1380_ssram

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